Complementary metal oxide semiconductor (CMOS) manufacturing processes are the most widely used semiconductor manufacturing processes and are recognized for their superior robustness and low cost in generating large volumes of product. Conventional CMOS processes are directed toward fabricating digital circuits, e.g., microprocessors, and the peripheral circuits, e.g., mixed-signal and radio frequency circuits. The use of CMOS sensors, however, has recently experienced rapid growth. CMOS sensors include image sensors, temperature sensors, and magnetic field sensors among many others. Additionally, many semiconductor sensors, such as pressure sensors or accelerometers, are either CMOS hybrids or CMOS systems monolithically integrated with microelectrical-mechanical systems (MEMS). Semiconductor sensors enable many new products and applications in automotive and consumer electronic market.
One major challenge in using CMOS processes for fabricating sensors is the limited absolute accuracy achieved with these sensors and the sensitivity of the devices to packaging and fabrication processes. For example, the offset in Hall sensors is influenced by the piezoresistance effect. The piezoresistance effect results from the mechanical stress on the chip which are not controlled in low cost packaging technologies, e.g., plastic packages as reported in Z. Randjelovic, “Low-power High Sensitivity Integrated Hall magnetic Sensor Microsystems,” PhD Thesis, EPFL, 2000; and S. Bellekom, “Origins of Offset in Conventional and Spinning-current Hall Plates,” PhD Thesis, Delft University, 1998. Similar effects limit the performance of many other sensors.
Layout techniques have been used in an attempt to mitigate various error sources. Mitigation techniques include manufacturing multiple devices on a single substrate with the theory that neighboring devices will cancel at least some of the errors introduced by the other device and/or the use of dummy devices. See, e.g., Z. Randjelovic; A. Hasting, “The Art of Analog Layout,” Prentice Hall, 2005; and J. Frounchi et al., “Integrated Hall sensor array microsystem,” ISSCC, p. 248-249, February 2001.
The effectiveness of the mitigation methods identified above is limited by constancy of the mechanical stress or process gradient on the chip. Specifically, to the extent the substrate exhibits a uniform gradient in a single dimension, neighboring devices will exhibit the same errors or offsets. Accordingly, by reversing the orientation of alternate devices, the offset realized in one device is eliminated by the reversed offset in the adjacent device.
In reality, however, sources of offset are not presented in a uniform gradient in a single dimension. Rather, the gradient varies within not only a single dimension, but in two dimensions, that is, both along the length of the substrate and the width of the substrate. Accordingly, neighboring devices exhibit different errors and the error of one device will not be completely cancelled by any one of the surrounding devices. Thus, sensor packages are typically costly and limited to use in applications depending on the offset tolerance of the application.
The non-linear stress exhibited by some sensors may be mitigated by other techniques. For example, the spinning current technique is generally used to cancel the remainder of offset errors in the specific case of Hall sensors. See, e.g., Bellekom; Frounchi; and J. van der Meer et al., “A Fully Integrated CMOS Hall Sensor with 3.65 μT 3σ Offset for Compass Applications,” ISSCC, p. 246-247, February 2005. The increased accuracy attainable in these other techniques, however, is limited by second order effects such as Joule Heating, Seebeck, and Peltier effects. These additional techniques further require increased costs for front-end electronics.
A need exists for CMOS sensors with improved accuracy without a significant increase in cost.